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LMK04832PAP/EM Datasheet(PDF) 79 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 79 Page - Texas Instruments |
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79 / 102 page  8.6.2.8.6 PLL2_DLD_CNT Table 8-76. PLL2_DLD_CNT[13:0] MSB LSB 0x16A[5:0] / PLL2_DLD_CNT[13:8] 0x16B[7:0] / PLL2_DLD_CNT[7:0] This register has the value of the PLL2 DLD counter. Table 8-77. Registers 0x16A and 0x16B REGISTER BIT NAME POR DEFAULT DESCRIPTION 0x16A 7 NA 0 Reserved 0x16A 5:0 PLL2_DLD _CNT[13:8] 32 The reference and feedback of PLL2 must be within the window of phase error as specified by PLL2_WND_SIZE for PLL2_DLD_CNT cycles before PLL2 digital lock detect is asserted. Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 0x16B 7:0 PLL2_DLD_CNT 0 2 (0x02) 2 3 (0x03) 3 ... ... 16,382 (0x3FFE) 16,382 16,383 (0x3FFF) 16,383 www.ti.com LMK04832-SEP SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: LMK04832-SEP |
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