LMK04832PAPSLASHEM datasheet(89/102 Pages) TI

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9.2.1 Design Requirements

Clocks outputs:

• 1x 122.88 MHz LVCMOS

• 1x 122.88 MHz HSDS

• 1x 245.76 MHz LVPECL

• 1x 983.04 MHz LVDS

• 1x 2949.12 MHz CML

For best performance, the highest possible phase detector frequency is used at PLL2. As such, a 122.88-MHz

VCXO is used. Assume that the 2949.12-MHz CML clock is the most performance critical one.

9.2.2 Detailed Design Procedure

TI has the TICSPRO and PLLatinum™ simulation tools that can be used to determine register values and design

the loop filter. CML and LVPECL output formats have the best noise floor, but consume more current, therefore it

is best to use these formats when noise floor matters. As for frequency planning, CLKOUT4 has the most critical

output, and this output has a strong interaction with the CLKOUT6. To avoid a strong interaction, the CLKOUT6

was not used in this example and a spur was added to the CLKOUT4. The 122.88-MHz HSDS clock could

potentially generate a lot of spurs and mixing products, so this HSDS clock was placed on the CLKOUT8 that

has the weakest interaction with the other channels.

9.2.2.1 Device Selection

Enter the required frequencies into the tools. In this design, VCO0 and VCO1 both meet the design

requirements. VCO0 offers a relatively improved VCO performance over VCO1. In this case, choose VCO0

for improved RMS jitter in the 12-kHz to 20-MHz integration range.

9.2.2.1.1 Clock Architect

Under the advanced tab of the Clock Architect, filtering of specific parts can be done using regular expressions

in the Part Filter box. [LMK04832.*] will filter for only the LMK04832 device (without brackets). More detailed

filters can be given such as the entire part name LMK04832_VCO0 to force an LMK04832 using VCO0 solution

if one is available.

9.2.2.2 Device Configuration and Simulation

The tools automatically configure the simulation to meet the input and output frequency requirements given, and

make assumptions about other parameters to give some default simulations. However, the user may chose to

make adjustments for more accurate simulations to their application. For example:

• Entering the VCO Gain of the external VCXO or possible external VCO used device.

• Adjust the charge pump current to help with loop filter component selection. Lower charge pump currents

result in smaller components but may increase impacts of leakage and at the lowest values reduce PLL

phase noise performance.

• Clock Architect allows loading a custom phase noise plot for reference or VCXO block. Typically, a custom

phase noise plot is entered for CLKin to match the reference phase noise to device; a phase noise plot for

the VCXO can additionally be provided to match the performance of VCXO used. For improved accuracy in

simulation and optimum loop filter design, be sure to load these custom noise profiles for use in application.

• The PLLatinum™ Simulation tool can also be used to design and simulate a loop filter.

9.2.2.3 Device Setup

Frequency Planning

• Even clock outputs have the simplest output path and lowest noise floor, so they were chosen.

• CLKOUT4 is used so therefore CLKOUT6 & CLKOUT7 should either not be used or at least be assigned the

same frequency as CLKOUT4.

• CLKOUT8 is used, so therefore CLKOUT10 & CLKOUT11 should either not be used or at least be assigned

the same frequency as CLKOUT8.

Output Formats

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LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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LMK04832PAP/EM Datasheet(PDF) 89 Page - Texas Instruments

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