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LMK04832PAP/EM Datasheet(PDF) 77 Page - Texas Instruments

Part # LMK04832PAP/EM
Description  LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner
PDF  102 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LMK04832PAP/EM Datasheet(HTML) 77 Page - Texas Instruments

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8.6.2.8.3 PLL2_N_CAL
PLL2_N_CAL[17:0]
PLL2 never uses 0-delay during frequency calibration. These registers contain the value of the PLL2 N divider
used with PLL2 pre-scaler during calibration for cascaded 0-delay mode. Once calibration is complete, PLL2 will
use the PLL2_N value. Cascaded 0-delay mode occurs when PLL2_NCLK_MUX = 1.
Table 8-71. PLL2_N_CAL[17:0]
MSB
—
LSB
0x163[1:0] / PLL2_N_CAL[17:16]
0x164[7:0] / PLL2_N_CAL[15:8]
0x165[7:0] / PLL2_N_CAL[7:0]
Table 8-72. Registers 0x163, 0x164, and 0x165
REGISTER
BIT
NAME
POR DEFAULT
DESCRIPTION
0x163
7:2
NA
0
Reserved
0x163
1:0
PLL2_N _CAL[17:16]
0
Field Value
Divide Value
0 (0x00)
Not Valid
0x164
7:0
PLL2_N_CAL[15:8]
0
1 (0x01)
1
2 (0x02)
2
0x165
7:0
PLL2_N_CAL[7:0]
12
...
...
262,143 (0x3FFFF)
262,143
8.6.2.8.4 PLL2_N
This register disables frequency calibration and sets the PLL2 N divider value. Programming register 0x168
starts a VCO calibration routine if PLL2_FCAL_DIS = 0.
Table 8-73. PLL2_N[17:0]
MSB
—
LSB
0x166[1:0] / PLL2_N[17:16]
0x167[7:0] / PLL2_N[15:8]
0x168[7:0] / PLL2_N[7:0]
Table 8-74. Registers 0x166, 0x167, and 0x168
REGISTER
BIT
NAME
POR DEFAULT
DESCRIPTION
0x166
7:3
NA
0
Reserved
0x166
2
PLL2_FCAL_DIS
0
Setting this to 1 disables PLL2 frequency calibration on
programming of register 0x168
0x166
1:0
PLL2_N[17:16]
0
Field Value
Divide Value
0 (0x00)
Not Valid
0x167
7:0
PLL2_N[15:8]
0
1 (0x01)
1
2 (0x02)
2
0x168
7:0
PLL2_N[7:0]
12
...
...
262,143 (0x3FFFF)
262,143
www.ti.com
LMK04832-SEP
SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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