LMK04832PAPSLASHEM datasheet(87/102 Pages) TI

87 / 102 page

Note

The signal level must conform to the requirements for the CLKin or OSCin pins listed in the Electrical

Characteristics table.

To support LOS functionality, CLKinX_BUF_TYPE must be set to MOS mode (CLKinX_BUF_TYPE

= 1) when AC-coupled. When AC coupling, if the 100-Ω termination is placed on the IC side of the

blocking capacitors, then the LOS functionality will not be valid.

Clock Source

Input

0.1 µF

0.1 µ F

CLKINx_P

CLKINx_N

Figure 9-4. CLKINx_P/CLKINx_N Single-Ended Termination

If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or

AC coupling may be used. If DC coupling is used, the CLKinX_BUF_TYPE should be set to MOS buffer

mode (CLKinX_BUF_TYPE = 1) and the voltage swing of the source must meet the specifications for DC-

coupled, MOS-mode clock inputs given in the Electrical Characteristics table. If AC coupling is used, the

CLKinX_BUF_TYPE should be set to the bipolar buffer mode (CLKinX_BUF_TYPE = 0). The voltage swing at

the input pins must meet the specifications for AC-coupled, bipolar mode clock inputs given in the Electrical

Characteristics table. In this case, some attenuation of the clock input level may be required. A simple resistive

divider circuit before the AC-coupling capacitor is sufficient.

LVCMOS/LVTTL

Clock Source

Input

0.1 µF

CLKINx_P

CLKINx_N

0.1 µF

Figure 9-5. DC-Coupled LVCMOS/LVTTL Reference Clock

9.1.5 OSCin Doubler for Best Phase Noise Performance

PLL2 OSCin input path includes an on-chip Frequency Doubler. To have the best phase noise performance, TI

recommends to maximize the PLL2 phase detector frequency. For example, using 122.88-MHz VCXO, PLL2

phase detector frequency can be increased to 245.76 MHz by setting PLL2_REF_2X_EN. Doubler path is a

high performance path for OSCin clock. For configuration where doubler cannot be used, TI recommends to use

Doubler and PLL2_RDIV = 2. To have deterministic phase relationship between input clock and output clocks,

0-delay modes should be used (nested 0-delay mode for dual loop configuration instead of cascaded 0-delay

mode).

9.1.6 Radiation Environments

9.1.6.1 Total Ionizing Dose

Radiation Hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level

specified in the ordering information. Testing and qualification of these product is done according to MIL-

STD-883, test method 1019.

www.ti.com

LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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