LMK04832PAPSLASHEM datasheet(44/102 Pages) TI

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8.6.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls

8.6.2.2.1 DCLKX_Y_DIV

The device clock divider can drive up to two outputs, an even (X) and an odd (Y) clock output. Divide is a 10 bit

number and split across two registers.

Table 8-15. DCLKX_Y_DIV Field Registers

MSB

LSB

0x0102[1:0] = DCLK0_1_DIV[9:8]

0x100[7:0] = DCLK0_1_DIV[7:0]

0x010A[1:0] = DCLK2_3_DIV[9:8]

0x108[7:0] = DCLK2_3_DIV[7:0]

0x0112[1:0] = DCLK4_5_DIV[9:8]

0x110[7:0] = DCLK4_5_DIV[7:0]

0x011A[1:0] = DCLK6_7_DIV[9:8]

0x118[7:0] = DCLK6_7_DIV[7:0]

0x0122[1:0] = DCLK8_9_DIV[9:8]

0x120[7:0] = DCLK8_9_DIV[7:0]

0x012A[1:0] = DCLK10_11_DIV[9:8]

0x128[7:0] = DCLK10_11_DIV[7:0]

0x0132[1:0] = DCLK12_13_DIV[9:8]

0x130[7:0] = DCLK12_13_DIV[7:0]

Table 8-16. Registers 0x100, 0x108, 0x110, 0x118, 0x120, 0x128, and 0x130

0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132

BIT

NAME

POR DEFAULT

DESCRIPTION

0x102,

0x10A,

0x112,

0x11A,

0x122,

0x12A, 0x132

1:0

DCLKX_Y_DIV[9:8]

X_Y = 0_1 → 2

X_Y = 2_3 → 4

X_Y = 4_5 → 8

X_Y = 6_7 → 8

X_Y = 8_9 → 8

X_Y = 10_11 → 8

X_Y = 12_13 → 2

DCLKX_Y_DIV sets the divide value for the clock output, the divide

may be even or odd. Both even or odd divides output a 50% duty

cycle clock if duty cycle correction (DCC) is enabled.

0x100,

0x108,

0x110, 0x118,

0x120,

0x128, and

0x130

7:0

DCLKX_Y_DIV[7:0]

Field Value

Divider Value

0 (0x00)

Reserved

1 (0x01)

1 (1)

2 (0x02)

...

1022 (0x3FE)

1022

1023 (0x3FF)

1023

(1)

Duty cycle correction must also be enabled, DCLKX_Y_DCC = 1.

LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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