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LMK04832PAP/EM Datasheet(PDF) 63 Page - Texas Instruments

Part # LMK04832PAP/EM
Description  LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner
PDF  102 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LMK04832PAP/EM Datasheet(HTML) 63 Page - Texas Instruments

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8.6.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
This register has CLKin_SEL1 controls and register readback SDIO pin type.
Table 8-45. Register 0x149
BIT
NAME
POR DEFAULT
DESCRIPTION
7
NA
0
Reserved
6
SDIO_RDBK_TYPE
1
Sets the SDIO pin to open drain when during SPI readback in 3 wire mode.
0: Output, push-pull
1: Output, open drain.
5:3
CLKin_SEL1_MUX
0
This set the output value of the CLKin_SEL1 pin. This register only applies if
CLKin_SEL1_TYPE is set to an output mode.
Field Value
Output Format
0 (0x00)
Logic Low
1 (0x01)
CLKin1 LOS
2 (0x02)
CLKin1 Selected
3 (0x03)
DAC Locked
4 (0x04)
DAC Low
5 (0x05)
DAC High
6 (0x06)
SPI Readback
7 (0x07)
Reserved
2:0
CLKin_SEL1_TYPE
2
This sets the IO type of the CLKin_SEL1 pin.
Field Value
Configuration
Function
0 (0x00)
Input
Input mode, see Input
Clock Switching -
Pin Select Mode for
description of input
mode.
1 (0x01)
Input with pullup resistor
2 (0x02)
Input with pulldown
resistor
3 (0x03)
Output (push-pull)
Output modes; see
the CLKin_SEL1_MUX
register for description of
outputs.
4 (0x04)
Output inverted (push-
pull)
5 (0x05)
Reserved
6 (0x06)
Output (open-drain)
www.ti.com
LMK04832-SEP
SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: LMK04832-SEP



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