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LMK04832PAP/EM Datasheet(PDF) 4 Page - Texas Instruments |
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LMK04832PAP/EM Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 102 page  Table 5-1. Pin Functions (continued) PIN I/O TYPE DESCRIPTION NO. NAME 3 CLKIN1_N I ANLG Reference Clock input port 1 for PLL1. FIN1_N External VCO input or clock distribution input. FBCLK_N Feedback input for external clock feedback input (0–delay mode). 4 VCC6_PLL1 – PWR Power supply for PLL1, charge pump 1, holdover DAC 5 CLKIN0_P I ANLG Reference Clock input port 0 for PLL1. 6 CLKIN0_N 7 VCC7_OSCOUT – PWR Power supply for OSCOUT pins. 8 OSCOUT_P I/O Programmable Buffered output of OSCIN pins CLKIN2_P Reference Clock input port 2 for PLL1. 9 OSCOUT_N I/O Programmable Buffered output of OSCIN pins CLKIN2_N Reference Clock input port 2 for PLL1. 10 VCC8_OSCIN – PWR Power supply for OSCIN 11 OSCIN_P I ANLG Feedback to PLL1 and reference input to PLL2. AC-coupled. 12 OSCIN_N 13 VCC9_CP2 – PWR Power supply for PLL2 charge pump. 14 CPOUT2 O ANLG Charge pump 2 output. 15 VCC10_PLL2 – PWR Power supply for PLL2. 16 STATUS_LD2 I/O Programmable Programmable status pin. 17 CLKOUT9_P O Programmable Clock output 9. For JESD204B/C systems suggest SYSREF Clock. (1) Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. 18 CLKOUT9_N 19 CLKOUT8_P O Programmable Clock output 8. For JESD204B/C systems suggest Device Clock. (1) Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. 20 CLKOUT8_N 21 VCC11_CG3 – PWR Power supply for clock outputs 8, 9, 10, and 11. 22 CLKOUT10_P O Programmable Clock output 10. For JESD204B/C systems suggest Device Clock. (1) Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. 23 CLKOUT10_N 24 CLKOUT11_P O Programmable Clock output 11. For JESD204B/C systems suggest SYSREF Clock. (1) Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. 25 CLKOUT11_N 26 CLKin_SEL0 I/O Programmable Programmable status pin. 27 CLKIN_SEL1 I/O Programmable Programmable status pin. 28 CLKOUT13_P O Programmable Clock output 13. For JESD204B/C systems suggest SYSREF Clock. (1) Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. 29 CLKOUT13_N 30 CLKOUT12_P O Programmable Clock output 12. For JESD204B/C systems suggest Device Clock.(1) Programmable formats: CML, LVPECL, LCPECL, or LVDS. 31 CLKOUT12_N 32 VCC12_CG0 – PWR Power supply for clock outputs 0, 1, 12, and 13. 33 CLKOUT0_P O Programmable Clock output 0. For JESD204B/C systems suggest Device Clock.(1) Programmable formats: CML, LVPECL, LCPECL, or LVDS. 34 CLKOUT0_N 35 CLKOUT1_P O Programmable Clock output 1. For JESD204B/C systems suggest SYSREF Clock. Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. 36 CLKOUT1_N 37 RESET/GPO I CMOS Device reset input or GPO 38 SYNC/ SYSREF_REQ I CMOS Synchronization input or SYSREF_REQ for requesting continuous SYSREF. 39 GND – GND This pin should be grounded. LMK04832-SEP SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LMK04832-SEP |
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