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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

123 of 224

www.dialog-semiconductor.com

12. I2C Interface

Overview

12.1

DA6021 is a slave-

only device that is mastered by the SoC. It resides off the SoC’s I2C. The slave device

implemented on DA6021 side is an asynchronous implementation and will support the high speed mode

(3.4MHz). Some of the main features for the I2C slave are:



DA6021 is accessed using a 7-bit addressing scheme.



I2C slave is not allowed to stretch the clock, and must be capable of being multi-mastered in a debug

environment.



The interface draws as minimum power when not actively reading/writing registers.



The slave adapts to the incoming frequency without any communication as the protocol for fast mode

and high speed mode is the same.



2 Slave Address are supported. Each address is targeting a 256 register page inside DA6021.



Sequential offset accesses within a single transaction (burst reads and writes) are not required.



Interface implementation is asynchronous.

Slave Addresses

12.2

DA6021 supports the standard I2C read and write functions. The configuration register space is divided into two

256-byte partitions. DA6021 supports five 7-bit device addresses to access each of the 256 byte partitions. Note

that in 8-bit format, these addresses correspond to 0xBC and 0xDC for writes, and 0xBD and 0xDD for reads.

In order to avoid conflict with the assigned addresses the slave addresses will be programmable via OTP.

Slave address

Read address

Write address

Device 1

0x5E

0xBC

0xBD

Device 2

0x6E

0xDC

0xDD

Table 88: I2C Slave Addresses

The slave addresses need to be locked in order to avoid that software can overwrite them and disable the

communication.

Protocol

12.3

Reads from PMIC registers follow the “combined protocol” as described in the I2C specification, in which the first

byte written is the register offset to be read, and the first byte read (after a repeat START condition) is the data

from that register offset. See the figures below for details. The following diagrams capture the different high-

speed and fast-speed transaction format/protocol

Figure 56: I2C Fast Speed Write

7b SLAVE

ADDRESS

R/W

8b DATA

A/A

7'h5E or 7'h6E

‘0’ (Write)

Reg. Offset

Reg. Data

A = Acknowledge (SDA LOW)

A = Not Acknowledge (SDA HIGH)

S = START Condition

P = STOP Condition

Master to Slave

Slave to Master

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