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PM73121 Datasheet(PDF) 101 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 101 Page - PMC-Sierra, Inc |
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101 / 223 page  PM73121 AAL1gator II PMC-Sierra, Inc. PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ 4.3.2 Memory Interface Signals 4.3.3 T1/E1 Interface Signals Table 7. Memory Interface Signals Signal Pin # Type* Reset Value* Description MEM_DATA(15:10) MEM_DATA(9:4) MEM_DATA(3:0) 235-230 228-223 221-218 Bi Z Memory Data Bits 15 to 0 form the 16-bit wide data bus to external memory. MEM_ADDR(16:15) MEM_ADDR(14) MEM_ADDR(13:8) MEM_ADDR(7:0) 215-214 211 208-203 201-194 Out Z Memory Address Data Bits 16 to 0 form the 17-bit wide address bus to external memory. Pulled up with an internal resistor. /MEM_OE 191 Out 1 Memory Output Enable is an active low signal that enables the SRAM to drive data. Maximum output current (IMAX) = 8 mA. /MEM_WE(0) 188 Out 1 Memory Write Enable Zero is an active low signal for the low-byte write. Maximum output current (I MAX) = 8 mA. /MEM_WE(1) 190 Out 1 Memory Write Enable One is an active low signal for the high-byte write. Maximum output current (I MAX) = 8 mA. /MEM_CS 192 Out 1 Memory Chip Select is an active low chip-select signal for external memory. Maximum output current (I MAX) = 8 mA. *Present when /RESET is asserted and SYS_CLK is being clocked. Table 8. T1/E1 Interface Signals Signals Pin # Type Reset Value* Description TL_FSYNC(7) TL_FSYNC(6) TL_FSYNC(5) TL_FSYNC(4) TL_FSYNC(3) TL_FSYNC(2) TL_FSYNC(1) TL_FSYNC(0) 155 142 130 114 102 83 71 52 In NA Transmit Line Frame Synchronization Bits 7 to 0 are the transmit frame synchronization indications from the framer devices in SDF-MF and SDF-FR modes. The lines originate from the corresponding framer devices 0 to 7. TL_CLK(7) TL_CLK(6) TL_CLK(5) TL_CLK(4) TL_CLK(3) TL_CLK(2) TL_CLK(1) TL_CLK(0) 156 143 131 115 103 84 72 54 Bi NA* Transmit Line Channel Clock Bits 7 to 0 are the clock lines for the eight T1/E1 lines. The bits clock the data from the AAL1gator II to the corresponding framer devices. In the UDF-HS mode, only line 0 is active. Depending on the value of TLCLK_OUTPUT_EN and the CLK_SOURCE bits, these pins are either outputs or inputs. If TLCLK_OUTPUT_EN is high, these pins are outputs and the clock is sourced internally at power up. This can later be changed by the CLK_SOURCE bits. Maximum output current (I MAX) = 8 mA. * If TLCLK_OUTPUT_EN is high, the pins output the RL_CLK during reset. |
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