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PM73121 Datasheet(PDF) 112 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 112 Page - PMC-Sierra, Inc |
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112 / 223 page ![]() PMC-Sierra, Inc. PM73121 AAL1gator II PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ 6.2 Receive Side Line Interface Timing Figure 59, Figure 60, Figure 61 on page 96, and Figure 62 on page 96 show the receiver transmits data to the lines for low-speed applications. These lines typically interface with the transmit input portion of the corresponding framer. The AAL1gator II drives the same signaling data onto TL_ SIG during each frame of a multiframe. Data is output off the rising edge of TL_CLK, and TL_ FSYNC and TL_MSYNC are sampled using the falling edge of TL_CLK. The timing parameters are explained in the tables following the figures. The format of signaling data on the TL_SIG output is dependent on the framer operating mode. When operating in T1 mode, the AAL1gator II drives signaling only on the lower four bits of each timeslot as shown in Table 15 on page 93 and Figure 60. In all cases, signaling data is driven on the TL_SIG pin for all frames of each multiframe. The rising edge of TL_FSYNC should occur only during the frame (F) bit of the T1 data stream. The rising edge of TL_MSYNC should occur only during the F bit that starts each 12-frame (SF) or 24-frame (ESF) multiframe. If a sync input occurs when it is not expected, the AAL1gator II will resync to the new structure. The sync pulses do not have to be driven every frame or multi- frame. Figure 59. Receive Side Low-Speed Interface Bit Timing Symbol Parameter Signals Min Max Unit Fc Clock frequency TL_CLK 15 MHz Tcp Clock pulse width TL_CLK 10 ns Tsu Clock setup TL_MSYNC, TL_FSYNC 5 ns Th Clock hold TL_MSYNC, TL_FSYNC 1 ns Tq Clock-to-output delay TL_SIG, TL_SER 2 14 ns Tsu Tcp Tcp Tcp Fc Fc Tcp Th Tq TL_CLK(i) TL_FSYNC(i) TL_MSYNC(i) TL_SIG(o) TL_SER(o) |
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