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PM73121 Datasheet(PDF) 114 Page - PMC-Sierra, Inc

Part # PM73121
Description  AAL1 Segmentation And Reassembly Processor
PDF  223 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM73121 Datasheet(HTML) 114 Page - PMC-Sierra, Inc

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PMC-Sierra, Inc.
PM73121 AAL1gator II
PMC-980620
,VVXH
AAL1 SAR Processor
Data Sheet
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6.3
Transmit UTOPIA Timing
6.3.1
TUTOPIA as the ATM Layer Device
The transmit ATM UTOPIA timing signals are compatible with the ATM Forum UTOPIA Level
1 byte-by-byte specification (refer to Appendix B, “References”, on page 203). Table 17 indicates
the transmit UTOPIA signal names and their corresponding UTOPIA designations. The interface
will not assert /TATM_EN at the beginning of a cell unless it has a full cell to send. After the
AAL1gator II detects /TATM_FULL asserted, it deasserts /TATM_EN two TATM_CLK cycles
later. Refer to section 3.4 “Transmit UTOPIA Interface Block (TUTOPIA)” on page 41 for addi-
tional information.
Figure 63 illustrates the transmit ATM UTOPIA timing.
Table 17.
Transmit Signal Names and Corresponding UTOPIA Designations
Signal Name
UTOPIA Name
TATM_DATA
TxDATA
TATM_SOC
TxSOC
/TATM_EN
TxEnb*
/TATM_FULL
TxFull*
TATM_CLK
TxClk
Figure 63.
Transmit UTOPIA ATM Timing
Symbol
Parameter
Signals
Min
Max
Unit
Fc
Clock frequency
TATM_CLK
33
MHz
Tdc
Clock duty cycle
TATM_CLK
45
55
%
Tsu
Clock setup
/TATM_FULL
5
ns
Th
Clock hold
/TATM_FULL
1
ns
Tq
Clock-to-output delay
TATM_SOC, /TATM_EN
2
12
ns
Tq
Clock-to-output delay
TATM_DATA
2
13
ns
Tdc
Tdc
Fc
Fc
Th
Tsu
Tq
53
01
02
03
04
05
06
07
TATM_CLK(i)
/TATM_FULL(i)
/TATM_EN(o)
TATM_SOC(o)
TATM_DATA(o)



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