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PM73121 Datasheet(PDF) 113 Page - PMC-Sierra, Inc

Part # PM73121
Description  AAL1 Segmentation And Reassembly Processor
PDF  223 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM73121 Datasheet(HTML) 113 Page - PMC-Sierra, Inc

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PMC-Sierra, Inc.
PM73121 AAL1gator II
PMC-980620
,VVXH
AAL1 SAR Processor
Data Sheet
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In E1 mode, data is driven on the lower four bits of each timeslot as shown in Table 16 on
page 94. Signaling data is driven on the TL_SIG pin for all frames of each multiframe. The
AAL1gator II treats all 32 timeslots the same. Although E1 data streams contain 30 timeslots of
channel data and 2 timeslots of control, data and signaling for all 32 timeslots are stored in mem-
ory.
In UDF-HS mode there is no structure and the data is driven using TL_CLK(0) as shown in
Figure 62.
Figure 60.
Receive Side T1 Interface Frame Timing
Figure 61.
Receive Side E1 Interface Timing
Figure 62.
Receive Side High-Speed Interface Timing
Symbol
Parameter
Signals
Min
Max
Unit
Fc
Clock frequency
TL_CLK(0)
45
MHz
Tcp
Clock pulse width
TL_CLK(0)
45
55
%
Tq
Clock-to-output delay
TL_SER(0)
2
13
ns
CHAN 24, FRAME 24
CHAN 24, FRAME 24
CHAN 1, FRAME 1
CHAN 1, FRAME 1
CD
C
D
AB
A
B
C
D
F
2
34
5
6
78
8
7
6
5
12
3
4
78
1
TL_CLK(i)
TL_FSYNC(i)
TL_MSYNC(i)
TL_SER(o)
TL_SIG(o)
CHAN 1, FRAME 0
CHAN 1, FRAME 0
CHAN 0, FRAME 0
CHAN 0, FRAME 0
78
2
3
4
5
6
7
8
2
3
4
5
6
7
8
11
1
C
D
A
B
CD
A
B
CDA
TL_CLK
TL_FSYNC
TL_MSYNC
TL_SER
TL_SIG
Tcp
Fc
Fc
Tcp
Tcp
Tcp
Tq
TL_CLK(i)
TL_SER(o)



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