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PM73121 Datasheet(PDF) 116 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 116 Page - PMC-Sierra, Inc |
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116 / 223 page  PMC-Sierra, Inc. PM73121 AAL1gator II PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ 6.3.3 TUTOPIA as the PHY Layer Device in Multi-PHY (MPHY) Mode The TUTOPIA block functions as a receive UTOPIA block when in MPHY mode. The receive MPHY UTOPIA timing signals are compatible with the ATM Forum UTOPIA Level 2 MPHY specification. Table 18 on page 98 indicates the AAL1gator II receive MPHY UTOPIA signal names and their corresponding UTOPIA designations. The AAL1gator II will not drive RPHY_ CLAV unless /RPHY_ADDR was low the previous cycle. The value driven is dependent on whether or not the AAL1gator II has a complete cell to send. RPHY_DATA and RPHY_SOC are tristate, except for the cycles following ones in which /RPHY_EN is active and the AAL1gator II was selected. The AAL1gator II is selected only if on the falling edge of /RPHY_EN, /RPHY_ ADDR is low. RPHY_SOC indicates the start of a new cell. RPHY_CLAV goes inactive one cycle after the last data byte has been output if /RPHY_ADDR is low at the time. Figure 65 shows the data output timing for the TUTOPIA block in MPHY mode. The timing parameters used in Figure 65 are defined in the table following the figure. All output timing delays assume a capaci- tive loading of 50 pF. Refer to section 3.4 “Transmit UTOPIA Interface Block (TUTOPIA)” on page 41 for additional information. Symbol Parameter Signal Min Max Unit RPHY_CLK frequency 33 MHz Tdc RPHY_CLK duty cycle 45 55 % Thd RPHY_CLK hold time /RPHY_EN 1 ns Tq RPHY_CLK-to-output delay RPHY_CLAV, RPHY_SOC 2 12 ns Tsu RPHY_CLK setup time /RPHY_EN 5 ns Tq RPHY_CLK-to-output delay RPHY_DATA 2 13 ns Figure 65. TUTOPIA MPHY Timing D1 D2 D3 Tq Tq Tq Tsu Thd Tdc Tdc RPHY_CLK(i) /RPHY_ADDR(i) RPHY_CLAV(o) RPHY_SOC(o) RPHY_DATA(o) /RPHY_EN(i) |
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