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GL843 Datasheet(PDF) 43 Page - GENESYS LOGIC

Part # GL843
Description  High Speed USB 2.0 With ADF 2-in-1 Scanner Controller
PDF  84 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL843 Datasheet(HTML) 43 Page - GENESYS LOGIC

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GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 43
1
Has received data number specified in Reg 88 from RS232.
Offset 50h ……..……..…………………..………..….………..……....…..….…. Default value = 8’h00
X
X
FERDA5
FERDA4
FERDA3
FERDA2
FERDA1
FERDA0
X
X
R/W
R/W
R/W
R/W
R/W
R/W
7-6 RESERVED
-
5-0 FERDA[5:0]
Address of control register of front-end in read operation.
Before reading control register of front-end (Reg 46, 47), designers have to
specify address of the control register by writing address to this port.
Offset 51h ……..……..…………………..………..….………..….…..…..…..…. Default value = 8’h00
X
X
FEWRA5
FEWRA4
FEWRA3
FEWRA2
FEWRA1
FEWRA0
X
X
R/W
R/W
R/W
R/W
R/W
R/W
7-6 RESERVED
-
5-0 FEWRA[5:0]
Address of control register of front-end in write operation.
Before writing control register of front-end (Reg 3A, 3B), designers have to
specify address of the control register by writing address to this port.
Offset 52h ……..……..…………………..………..….………..….…..…..…..…. Default value = 8’h00
X
X
X
RHI4
RHI3
RHI2
RHI1
RHI0
X
X
X
R/W
R/W
R/W
R/W
R/W
7-5 RESERVED
-
4-0 RHI[4:0]
The latch point for high-byte of R channel of AFE in every pixel.
For example, if a system is designed to have 12 clocks/pixel, and designer wants
to latch the high-byte of R channel at 1’st clock in every pixel, designer has to fill
‘00001’ to RHI [4:0].
Offset 53h ……..……..…………………..………..….………..….…..…..…..…. Default value = 8’h00
X
X
X
RLOW4
RLOW3
RLOW2
RLOW1
RLOW0
X
X
X
R/W
R/W
R/W
R/W
R/W
7-5 RESERVED
-
4-0 RLOW[4:0]
The latch point for low-byte of R channel of AFE in every pixel
For example, if a system is designed to have 12 clocks/pixel, and designer wants
to latch the high-byte of R channel at 1’st clock in every pixel, designer has to fill
‘00001’ to RHI [4:0].
Offset 54h ……..……..…………………..………..….………..….…..…..…..…. Default value = 8’h00
X
X
X
GHI4
GHI3
GHI2
GHI1
GHI0
X
X
X
R/W
R/W
R/W
R/W
R/W
7-5 RESERVED
-
4-0 GHI[4:0]
The latch point for high-byte of G channel of AFE in every pixel.



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