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GL843 Datasheet(PDF) 52 Page - GENESYS LOGIC

Part # GL843
Description  High Speed USB 2.0 With ADF 2-in-1 Scanner Controller
PDF  84 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL843 Datasheet(HTML) 52 Page - GENESYS LOGIC

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GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 52
Offset 70h ……..………………………..………..….………..….………..…..…. Default value = 8’h06
X
X
X
RSH4
RSH3
RSH2
RSH1
RSH0
X
X
X
R/W
R/W
R/W
R/W
R/W
7-5 RESERVED
-
4-0 RSH[4:0]
Rising edge position of CCD RS.
Offset 71h ……..………………………..………..….………..….………..…..…. Default value = 8’h08
X
X
X
RSL4
RSL3
RSL2
RSL1
RSL0
X
X
X
R/W
R/W
R/W
R/W
R/W
7-5 RESERVED
-
4-0 RSL[4:0]
Falling edge position of CCD RS.
(1) Color, gray or line-art: 12 clocks(phase)/pixel
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
CCD RS : RSH=08H
RSL=0BH
Note: 16 clocks(phase)/pixel and 18 clocks(phase)/pixel modes are similar to 12 clocks(phase)/pixel mode.
Offset 72h ……..………………………..………..….………..….………..…..…. Default value = 8’h08
X
X
X
CPH4
CPH3
CPH2
CPH1
CPH0
X
X
X
R/W
R/W
R/W
R/W
R/W
7-5 RESERVED
-
4-0 CPH[4:0]
Rising edge position of CCD CP.
Offset 73h …….………………………..………..….………..….………..…..…. Default value = 8’h0A
X
X
X
CPL4
CPL3
CPL2
CPL1
CPL0
X
X
X
R/W
R/W
R/W
R/W
R/W
7-5 RESERVED
-
4-0 CPL[4:0]
Falling edge position of CCD CP.
(1) Color, gray or line-art: 12 clocks(phase)/pixel
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
CCD CP : CPH=0AH
CPL=01H
Note: 16 clocks(phase)/pixel and 18 clocks(phase)/pixel modes are similar to 12 clocks(phase)/pixel mode.



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