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GL843 Datasheet(PDF) 53 Page - GENESYS LOGIC

Part # GL843
Description  High Speed USB 2.0 With ADF 2-in-1 Scanner Controller
PDF  84 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL843 Datasheet(HTML) 53 Page - GENESYS LOGIC

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GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 53
Offset 74h ……..……..………………..………..…...………..….………..…..…. Default value = 8’h00
X
X
X
X
X
X
CK1MAP17 CK1MAP16
X
X
X
X
X
X
R/W
R/W
7-2 RESERVED
-
1-0 CK1MAP[17:16] Bits mapping setting for CCD clock 1 or 2.
Offset 75h ……..……..………………..……..…..….………..….………..…..…. Default value = 8’h00
CK1MAP15 CK1MAP14 CK1MAP13 CK1MAP12 CK1MAP11 CK1MAP10 CK1MAP9 CK1MAP8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 CK1MAP[15:8] Bits mapping setting for CCD clock 1 or 2.
Offset 76h ……..……..………………..………....….………..….………..…..…. Default value = 8’h00
CK1MAP7 CK1MAP6 CK1MAP5 CK1MAP4 CK1MAP3 CK1MAP2 CK1MAP1 CK1MAP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 CK1MAP[7:0]
Bits mapping setting for CCD clock 1 or 2.
Offset 77h ……..……..………………..………..…...………..….………..…..…. Default value = 8’h00
X
X
X
X
X
X
CK3MAP17 CK3MAP16
X
X
X
X
X
X
R/W
R/W
7-2 RESERVED
-
1-0 CK3MAP[17:16] Bits mapping setting for CCD clock 3.
Offset 78h ……..……..………………..……..…..….………..….………..…..…. Default value = 8’h00
CK3MAP15 CK3MAP14 CK3MAP13 CK3MAP12 CK3MAP11 CK3MAP10 CK3MAP9 CK3MAP8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 CK3MAP[15:8] Bits mapping setting for CCD clock 3.
Offset 79h ……..……..………………..………....….………..….………..…..…. Default value = 8’h00
CK3MAP7 CK3MAP6 CK3MAP5 CK3MAP4 CK3MAP3 CK3MAP2 CK3MAP1 CK3MAP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 CK3MAP[7:0]
Bits mapping setting for CCD clock 3.
Offset 7Ah ……..……..……………..………..…...………..….………..…..…. Default value = 8’h00
X
X
X
X
X
X
CK4MAP17 CK4MAP16
X
X
X
X
X
X
R/W
R/W
7-2 RESERVED
-
1-0 CK4MAP[17:16] Bits mapping setting for CCD clock 4.



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