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GL843 Datasheet(PDF) 45 Page - GENESYS LOGIC |
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GL843 Datasheet(HTML) 45 Page - GENESYS LOGIC |
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45 / 84 page ![]() GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 45 Offset 59h ……..……..…………………..………..….………..….…..…..…..…. Default value = 8’h00 BSMP4 BSMP3 BSMP2 BSMP1 BSMP0 BSMPW2 BSMPW1 BSMPW0 R/W R/W R/W R/W R/W R/W R/W R/W 7-3 BSMP[4:0] Rising edge position of dark voltage sampling for AFE. 2-0 BSMPW[2:0] Pulse width of dark voltage sampling. (1). Color, gray or line-art : 12 clocks (phase)/pixel mode 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 AFE BSMP Reg59=52H : BSMP[4:0]=10H BSMPW[2:0]=2H Note: 16 clocks (phase)/pixel and 18 clocks(phase)/pixel modes are similar to 12 clocks(phase)/pixel mode. Offset 5Ah ……..……..………………..………..….………..….…..…..…..…. Default value = 8’h00 ADCLKINV RLCSEL CDSREF1 CDSREF0 RLC3 RLC2 RLC1 RLC0 R/W R/W R/W R/W R/W R/W R/W R/W 7 ADCLKINV 0 ADC clock in not reversed. 1 ADC clock is reversed. 6 RLCSEL 0 Do not select. 1 Select reset level clamp on a pixel-by-pixel basis. 5-4 CDSREF[1:0] Front-end CDS reference for line rate scanning type. 3-0 RLC[3:0] Front-end RLC for line rate scanning type. Offset 5Bh ……..……..………………..………..….………..….…..…..…..…. Default value = 8’h00 X MTRTBL GMMADDR13 GMMADDR12 GMMADDR11 GMMADDR10 GMMADDR9 GMMADDR8 X R/W R/W R/W R/W R/W R/W R/W 7 RESERVED - 6 MTRTBL 0 To write gamma tables address by GMMADDR[12:0] 1 To write motor tables address by GMMADDR[12:0] 5-0 GMMADDR[13:8] Start address for downloading gamma or motor tables (in word) Offset 5Ch ……..……..………………..………..….………..….…..…..…..…. Default value = 8’h00 GMMADDR7 GMMADDR6 GMMADDR5 GMMADDR4 GMMADDR3 GMMADDR2 GMMADDR1 GMMADDR0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 GMMADDR[7:0] Start address for downloading gamma or motor tables (in word) Offset 5Dh ……..……..………………..………..….………..….…..…..…..…. Default value = 8’h00 HISPD7 HISPD6 HISPD5 HISPD4 HISPD3 HISPD2 HISPD1 HISPD0 R/W R/W R/W R/W R/W R/W R/W R/W |
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