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GL843 Datasheet(PDF) 15 Page - GENESYS LOGIC |
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GL843 Datasheet(HTML) 15 Page - GENESYS LOGIC |
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15 / 84 page ![]() GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 15 CCD_TGG O CCD Transfer gate clock for G channel CCD_TGB O CCD Transfer gate clock for B channel LAMP_SW O Flatbed lamp power control or CIS Red LED array control XPA_SW O Transparency lamp power control or CIS Green LED array control LED_B O CIS Blue LED array control Pin Name Type Description OP7~0 I AFE digital data input SEN O Serial interface load pulse SCLK O Serial interface clock output SDI O Serial data output SDO I Serial data input BSMP O Video sample synchronization pulse VSMP/CDSCLK2 O Video sample synchronization pulse MCLK/ADCCLK O Master clock. Pin Name Type Description DBUS15~0 I/O DRAM data bus ABUS12~0 O DRAM address bus RASJ SDRAM row address strobe CASJ O SDRAM column address strobe WEJ O SDRAM write enable BANK0~1 O SDRAM bank select CKE O SDRAM clock enable RAMCLK O SDRAM clock Pin Name Type Description X1 I Clock input for crystal (12MHz) X2 I/O Clock output for crystal EXTRST_ I Hardware reset input |
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