TMPR3916 datasheet(107/225 Pages) TOSHIBA

107 / 225 page

Chapter 4 Interrupt Controller (INTC)

Preliminary

4-2

4.2

Registers

Name

Phys. Address (hex)

Function

IRQR

1C04 0000

Indicates interrupt sources

IMASKR

1C04 0004

Enables/ disables interrupts

ILEXT

1C04 0008

Edge/ level detection of external interrupts

Interrupt Request Register (IRQR), Interrupt Mask Register (IMASKR)

IRQR:

If an interrupt occurs, the corresponding bit is set to 1.

Writing 0 to a bit resets the contents.

Writing 1 to a bit does not change the contents.

IMASKR:

1 = enables interrupt

0 = disables interrupt (an incoming interrupt will be stored in IRQR, but no interrupt

request will be sent to CPU)

Bit

3130

292827

262524

Name

EXT2

EXT1

EXT0

GDC

DMAC1

DMAC0

Bit

2322

212019

181716

Name

MPWM

(1)

SEIEXC

CAN1EXC

CAN0EXC

SIO3EXC

SIO2EXC

SIO1EXC

SIO0EXC

Bit

1514

131211

Name

PWM

PORT

SEITX

SEIRX

CAN1TX

CAN1RX

CAN0TX

CAN0RX

Bit

543

210

Name

SIO3TX

SIO3RX

SIO2TX

SIO2RX

SIO1TX

SIO1RX

SIO0TX

SIO0RX

(1) Only in IMASKR, in IRQR this bit is wired to zero

Bit

Name

Cause of Interrupt

Reset

Value

R/W

EXT2

External interrupt 2

0R/W

EXT1

External interrupt 1

0R/W

EXT0

External interrupt 0

0R/W

GDC

Vertical or horizontal sync. on GDC

0R/W

DMAC1

DMA on channel 1 finished or error on channel 1

0R/W

DMAC0

DMA on channel 0 finished or error on channel 0

0R/W

Periodic timer 1

0R/W

Periodic timer 0

0R/W

MPWM

Overflow on PWM timer enable

(only in IMASKR, in IRQR this bit is wired to zero)

R/W

SEI EXC

Exception during TXSEI transfer

0R/W

CAN1 EXC

Status change in TXCAN1

0R/W

CAN0 EXC

Status change in TXCAN0

0R/W

SIO3 EXC

Exception during serial I/O on UART channel 3

0R/W

SIO2 EXC

Exception during serial I/O on UART channel 2

0R/W

SIO1 EXC

Exception during serial I/O on UART channel 1

0R/W

SIO0 EXC

Exception during serial I/O on UART channel 0

0R/W

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