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TMPR3916 Datasheet(PDF) 108 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 108 Page - Toshiba Semiconductor |
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108 / 225 page ![]() Chapter 4 Interrupt Controller (INTC) Preliminary 4-3 Bit Name Cause of Interrupt Reset Value R/W 15 PWM PWM counter reached compare value or overflow of PWM counter if enabled by bit 23 of IMASKR 0 R/W 14 PORT Interrupt from PORT module 0R/W 13 SEI TX Transmission on TXSEI finished 0R/W 12 SEI RX Reception on TXSEI finished 0R/W 11 CAN1 TX Transmission on TXCAN1 finished 0R/W 10 CAN1 RX Reception on TXCAN1 finished 0R/W 9 CAN0 TX Transmission on TXCAN0 finished 0R/W 8 CAN0 RX Reception on TXCAN0 finished 0R/W 7 SIO3 TX Transmission on UART channel 3 finished 0R/W 6 SIO3 RX Reception on UART channel 3 finished 0R/W 5 SIO2 TX Transmission on UART channel 2 finished 0R/W 4 SIO2 RX Reception on UART channel 2 finished 0R/W 3 SIO1 TX Transmission on UART channel 1 finished 0R/W 2 SIO1 RX Reception on UART channel 1 finished 0R/W 1 SIO0 TX Transmission on UART channel 0 finished 0R/W 0 SIO0 RX Reception on UART channel 0 finished 0R/W ILEXT The register ILEXT controls edge or level detection of all external interrupt pins. When edge detection is enabled, an interrupt is caused on falling edge. When level detection is enabled, an interrupt is caused on low level. On level detection the bits in IRQR show the current level of the external interrupt pin. Before you can clear the interrupt, the external interrupt signal must be set to 1. Bit 31302928 27 0 Name LEXT2 LEXT1 LEXT0 Bit Name Function Reset Value R/W 31 Wired to zero 0R 30 LEXT2 0 = Edge detection on external interrupt 2 (falling edge) 1 = Level detection on external interrupt 2 (low level) 0 R/W 29 LEXT1 0 = Edge detection on external interrupt 1 (falling edge) 1 = Level detection on external interrupt 1 (low level) 0 R/W 28 LEXT0 0 = Edge detection on external interrupt 0 (falling edge) 1 = Level detection on external interrupt 0 (low level) 0 R/W 27:0 Wired to zero 0R |
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