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TMPR3916 Datasheet(PDF) 165 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 165 Page - Toshiba Semiconductor |
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165 / 225 page ![]() Chapter 9 Synchronous Serial I/O (TXSEI) Preliminary 9-10 system clock. When writing to the SESS register while the shift buffer contains a message, which is waiting to be transferred, this message will be sent immediately, since the counter is cleared to “0”. The slave select space can be calculated using the following formula: Pre-transfer time: SYS SSC_PRE f SESS t + = 2 (range: 33.33 ns up to 4.28 µs at 60 MHz system clock) Post-transfer time: SYS SSC_POST f SESS t + = 3 (range: 50 ns up to 4.3 µs at 60 MHz system clock) The Slave Select Space Timer can be disabled by setting this register to “0”. The minimum time between setting the slave select signal and starting the transfer is 2 system clock cycles and the minimum time between the transfer end and deactivating the slave select signal is 3 system clock cycles. This is the case when SESS is set to “0”. The minimum time between two consecutive transfers is the sum of the minimum values of tSCC_PRE, tIFS and tSCC_POST: this is 6 system clock cycles. |
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