TMPR3916 datasheet(163/225 Pages) TOSHIBA

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Chapter 9 Synchronous Serial I/O (TXSEI)

Preliminary

9-8

As an example, some common settings for fSYS = 60 MHz are shown in the table below:

SER Setting

SEI Clock Rate (fSEI)

Sustained Peak

Data Rate

half-duplex

Sustained Peak

Data Rate

full-duplex

0x00

Invalid setting

0x01

15 MHz

15 Mbps

30 Mbps

0x02

10 MHz

10 Mbps

20 Mbps

0x03

7.5 MHz

7.5 Mbps

15 Mbps

0x04

6 MHz

6 Mbps

12 Mbps

0x05

5 MHz

5 Mbps

10 Mbps

0x09

3 MHz

3 Mbps

6 Mbps

0x13

1.5 MHz

1.5 Mbps

3 Mbps

0xFF

117.1875 kHz

117.1875 kbps

234.375 kbps

In slave mode, the setting is ignored and the clock is derived from the clock on the SEI bus.

Note: Due to the internal over-sampling, if the module is operated in slave mode, the input

baud-rate must be slightly less than 1/8 of the input system clock to the module.

(e.g. 60 MHz system input clock => SPI slave baud rate max. 7.25 Mbps)

SEI Inter Frame Space Register (SEFS)

Bit

3130

262524

Name



Bit

2322

212019

181716

Name



Bit

1514

131211

Name



IFS[9:8]

Bit

543

Name

IFS[7:0]

Bit

Name

Function

Reset

Value

R/W

31:10



Unused

0x000000

9:0

IFS

Inter frame space: Time between two consecutive transmission

frames

R/W

This register is used to configure the amount of time, which is inserted between two consecutive frames.

The time is guaranteed by an internal 10-bit down counter. The counter can be operated with or without

prescaler. The IFSPSE bit of the SECR0 register determines whether the prescaler should be used or not.

When operating without prescaler, the counter runs on SEI system clock. When operating with prescaler, the

counter runs on 1/32 of SEI system clock.

TMPR3916 Datasheet(PDF) 163 Page - Toshiba Semiconductor

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