TMPR3916 datasheet(159/225 Pages) TOSHIBA

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Chapter 9 Synchronous Serial I/O (TXSEI)

Preliminary

9-4

SEI Master Control Register (SEMCR)

Bit

3130

262524

Name



Bit

2322

212019

181716

Name



Bit

1514

131211

Name



Bit

543

210

Name

OPMODE



LOOP

SESTP

BCLR

Bit

Name

Function

Reset

Value

R/W

31:8



Unused

0x000000

7:6

OPMODE

Operation Mode

00 = Don’t care. Writing this value to the OPMODE bits doesn’t

change anything

01 = Configuration Mode:

Use this mode to change the settings of the bits MSTR, SBOS,

SPOL and SPHA in SECR0 and also the SECR1 register.

10 = Active Mode: normal operation mode

11 = Reserved. Do not use this setting

In Configuration Mode the SESTP and LOOP bit and also the

receive and transmit FIFO will be cleared. The master and slave

control modules will be kept in reset. Running transfers are

immediately aborted, even within the current frame.

R/W

5:3



Wired to zero

000

LOOP

Loop Enable:

If TXSEI is configured as a Master, this bit can be used to switch a

loop-back from the TX to the RX pin for diagnostic purpose. It could

be set only when the TXSEI is in active mode and configured as a

master. Setting the TXSEI in configuration mode will clear this bit.

0 = Loop disabled, normal operation

1 = Loop enabled

R/W

SESTP

SEI Stop

This bit is used only during master mode. If this flag is asserted, the

module will stop the transfer after the current frame has been

completed. This bit could be set only when the TXSEI is in active

mode and configured as a master. Setting the TXSEI in

configuration mode will clear this bit.

0 = Normal operation

1 = Module will stop after completion of the current transfer

R/W

BCLR

SEI Buffer Clear

This flag is used to clear the receive and transmit FIFO and can only

be used in master mode. The internal buffers can only be cleared, if

the module is already in stop mode. In this case, the FIFO logic can

be reset by writing a “1” value to this bit. The module can be taken

out of the stop mode in the same access.

A stop of TXSEI and clearance of the buffers might become

necessary to guarantee a fast response to events. It is

recommended to wait until the TXSEI module is idle (SIDLE=1)

before activating BCLR.

This bit will always be read as “0”.

R/W

TMPR3916 Datasheet(PDF) 159 Page - Toshiba Semiconductor

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