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TMPR3916 Datasheet(PDF) 212 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 212 Page - Toshiba Semiconductor |
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212 / 225 page  Chapter 11 Electrical Characteristics Preliminary 11-13 SCLK (SPOL=0) SCLK (SPOL=1) RX (output) TX (input) SS (output) invalid valid valid 1/fSEIS tSOD tSOH tCTDT tSSDV valid tSIS tSIH valid Figure 11.12.4 Timing Diagram for TXSEI Timing (Slave, SPHASE = 1) Parameter Symbol Min Typ Max Unit Slave Mode SEI Clock Frequency fSEIS 7.25 (1) MHz Clock to Data Valid Time tSOD 20 ns Clock to Data Invalid Time tSOH 0 ns Slave Data in Setup Time tSIS 20 ns Slave Data in Hold Time tSIH 5 ns Slave Select to Data Valid Time tSSDV 50 ns Slave Select to Clock tSSTC 3/fSYS ns Consecutive Transfer Delay Time (2) tCTDT 1/fSEIS ns Load on SEI Interface Signals CIF 50 pF (1) At 60 MHz system clock. In general: 1/8 of the system clock frequency. (2) fSYS refers to the TMPR3916 system clock (usually 60 MHz). (3) For SPHASE = 1 the slave does not require to be deselected between consecutive transfers. |
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