TMPR3916 datasheet(219/225 Pages) TOSHIBA

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Chapter 12 Package

Preliminary

12-6

Classification

Pin Name

Pin Function

CS5*

The chip select signal 5 will be asserted if an access to the

address range specified in the RCCR5 register will take place.

CS4*

The chip select signal 4 will be asserted if an access to the

address range specified in the RCCR4 register will take place.

CS3*

The chip select signal 3 will be asserted if an access to the

address range specified in the RCCR3 register will take place.

CS2*

The chip select signal 2 will be asserted if an access to the

address range specified in the RCCR2 register will take place.

HSYNC*

Horizontal sync signal input/output pin.

VSYNC*/CSYNC*

Vertical sync signal input/output pin or the composite sync signal

output pin.

The composite sync signal is the logic EX-NOR (exclusive nor)

operation on signals HSYNC* and VSYNC*

HDISP

While the viewable area of the current line is output by the GDC

the HDISP is set to logic one. Data can be read with one cycle

latency to this signal.

DOTCLK

Dot clock input/output pin. The dot clock is the reference clock for

the display. This clock is either input to or output by the

TMPR3916F.

PIO15/Digital R Out[5]

PIO14/Digital R Out[4]

PIO13/Digital R Out[3]

PIO12/Digital R Out[2]

PIO11/Digital R Out[1]

The general purpose input/output signals PIO11 to PIO15 (5bit)

can be switched in that way that the red intensity of the current

pixel is output. PIO15/Digital R Out[5] is the MSB.

PIO10/Digital G Out[5]

PIO9/Digital G Out[4]

PIO8/Digital G Out[3]

PIO7/Digital G Out[2]

PIO6/Digital G Out[1]

The general purpose input/output signals PIO6 to PIO10 (5 bit) can

be switched in that way that the green intensity of the current pixel

is output. PIO10/Digital G Out[5] is the MSB.

PIO5/Digital B Out[5]

PIO4/Digital B Out[4]

PIO3/Digital B Out[3]

PIO2/Digital B Out[2]

PIO1/Digital B Out[1]

PIO0/Digital B Out[0]

The general purpose input/output signals PIO0 to PIO5 (6 bit) can

be switched in that way that the blue intensity of the current pixel is

output. PIO5/Digital B Out[5] is the MSB.

ROUT

GOUT

BOUT

Output pins for the three primary color video (analog) signals used

as color source for display.

ROUT is the red video signal output pin, GOUT the green and

BOUT the blue. All these signal are analog signals output by the

VIEWDAC.

VBS

This terminal is used for noise rejection of DAC’s current

adjustment bias. It is recommended to connect a capacitance of

0.1*F to the ground.

VREF

External voltage reference-bias input for the digital-to-analog

converter.

GDC

FSADJ

Current-mirror output. This pin is used to set the current level in the

DAC outputs via an internal current-mirror. This pin is usually

connected to ground via a 745 Ohm resistor.

DREQ0

External DMA request signal.

DMAC

DACK0

DMA acknowledge signal output pin.

TX(CAN1)

Transmit pin of CAN channel 1

RX(CAN1)

Receive pin of CAN channel 1

TX(CAN0)

Transmit pin of CAN channel 0

TXCAN

RX(CAN0)

Receive pin of CAN channel 0

PIO18/TX(SEI)/TX(SIO0)

In master mode this pin is the data output of the SEI interface. In

slave mode this is the data input pin of the SEI interface.

PIO17/RX(SEI)/RX(SIO0)

In master mode this pin is the data input pin of the TXSEI device.

In slave mode this pin is the data output.

TXSEI

PIO16/CLK(SEI)/CLK(SIO)

In master mode the clock is output during transmission from the

TXSEI module. In slave mode the clock is received from the device

the TMPR3916F is communicating with.

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