TMPR3916 datasheet(218/225 Pages) TOSHIBA

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Chapter 12 Package

Preliminary

12-5

12.2 Pin Functions

Classification

Pin Name

Pin Function

A[26:2]

Address signal output pins.

The A26 pin has a special functionality. The level supplied to this

pin is latched with the rising edge of the RESET* signal. The level

determines whether to boot from a device with 16-bit or 32-bit

width. Supplying “high” lets the TMPR3916F boot from a 16-bit

device.

BE[3:0]*

Byte Enable output pins

The byte enable signals are used to select the bytes within the

word, which are accessed by the current write or read access.

The following list shows the relationship between byte enable

signals and the valid bytes on the data bus.

BE*[0] low => D[7:0] valid

BE*[1] low => D[15:8] valid

BE*[2] low => D[23:16] valid

BE*[3] low => D[31:24] valid

D[31:0]

Data input/output pins

RD*

The RD* signal is asserted during a read access to the external

bus interface.

WR*

The WR* signal is asserted during a write access to the external

bus interface.

LAST*

The LAST* signal is asserted if the final data of the current bus

operation is read or written.

BSTART*

The BSTART* signal is asserted for one cycle at the beginning of

an external bus interface access.

BURST*

The BURST* signal indicates that the current access is a burst

access.

BUSERR*

Bus Error input pin.

If an error occurs during the current transaction the external device

has the opportunity to signal this event to the TMPR3916F by

asserting the BUSERR* signal. Thereupon the TMPR3916F will

finish the access and will create a bus-error exception.

ACK*

Acknowledge signal input pin.

During a read access the external device acknowledges data-

transfers of a transaction by asserting the ACK* signal. The data

on the external bus interface will be sampled on the rising edge of

system clock.

During a write access the external device signals the TMPR3916F

that the data was captured by asserting the ACK* signal. The

TMPR3916F will complete the transaction.

CORE

RESET*

If a low level is applied to the RESET* signal the chip will go into

the reset state.

XTAL1

Input pin for the crystal.

XTAL2

Feedback output pin for the crystal.

SYSCLK

Output of system clock, which is the reference clock for bus

operation.

PLLOFF*

Master clock switching pin.

Inputting a “High” signal to this pin uses the built-in PLL circuit as

the master clock. Master clock frequency is eight times the external

clock. Inputting a low signal to this pin halts the built-in PLL circuit

oscillation and uses the external clock as master clock.

Clock Generator

CLKEN

The clock enable pin enables supply of crystal input to internal

PLL. This signal is high active.

CS1*

Chip select 1* signal for the external SDRAM device.

CS0*

Chip select 0* signal for the external SDRAM device.

RAS*

CAS*

WE*

The three signals row access strobe (RAS*), column access strobe

(CAS*) and write enable (WE*) are used to supply the SDRAM

with commands.

SDRAM

CKE

The clock enable pin is an output to SDRAM used for power saving

purposes.

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