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Avance Logic Inc.
ALS300
21
Bit 4:
0
single cycle DMA request
1
block cycle DMA request
Bit 3:
0
block cycle DMA requset when PCM FIFO is
not full : playback
not empty: record
1
DMA requset when PCM FIFO is
less then half full during playback or
less then half empty during recording
Bit 2
0
IRQ controlled 90h command (SB16 version)
1
FIFO controlled 90h command (SBPRO version)
BIT 1
0
IRQ controled continuous DMA mode
1
FIFO controlled continuous DMA mode
CR2
MISC.control
Default 00h
Read/write
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Read AS 1
Bit 3
reserved, read as 0
Bit 2
Reserved
Bit 1
reserved, read as 0
Bit 0
Reserved,(read as 0)
CR3
configuration
Default 23h
Bit 7-2
read/write
Bit 1-0
read only
Bit 6
read only
Bit 7
Reserved
Bit 6
E
2PROM control (Read only)
Bit 5
internal/external MPU401 midi output select
Bit 4
Reserved
Bit 3
reserved
Bit 2
reserved
Bit 1,0
chip version number (read as 11)
Bit 1
Bit 0
0
0
ALS007SP
01ALS100
1
0
ALS007/WTA2000
1
1
ALS200/ALS110//ALS120/ALS300
Power up input value
MIDIOUT,ROMCS is tri-state with internal 50K pull low resisters when power up reset.
MIDIOUT
0
external 10K pull down
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