Avance Logic Inc.
ALS300
51
GCR86 Default XXXXXXXXh
Mic record starting address
Bit
Type
Function
31:2
R/W
Mic-In starting address SA[31..2]
1:0
Reserved
GCR87 Default XXXXXXXXh
Mic record end address
Bit
Type
Function
31:2
R/W
Mic-In end address EA[31..2]
1:0
Reserved
GCR88 Default : 0000XXXXh
Mic record control
Bit
Type
Function
31:22
Reserved
21
R/W
MICIN FIFO threshold control 0 : 4 DW 1 : 2 DW
20:18
Reserved
17
R/W
MICIN FIFO control 0 : Normal 1 : Pause
16
R/W
Mic-In transfer control 0 : Stop 1 : start
15:2
R/W
Mic-In block length BL[15..2]
1:0
R
Reserved, Read as 1
nWhen (no. of byte in Mic-In FIFO) ≥ threshold,ALS300 will generate a request to
bus master for data transfer until Mic-In FIFO is empty. The bus master will transfer
data from ALS300 to system memory if enabled by bit 16.
oBlock length = (# of data byte ) - 1 (ex. 0FFFh→ 4K bytes)
ALS300 will generate an interrupt for every specified block size transfered.
GCR89 Default XXXXXXXXh
DRAM-Write starting address
Bit
Type
Function
31:2
R/W
DRAM-Write starting address SA[31..2]
1:0
Reserved
GCR8A Default XXXXXXXXh
DRAM-Write end address
Bit
Type
Function
31:2
R/W
DRAM-Write end address EA[31..2]
1:0
Reserved
nAfter whole buffer is accessed, GCR8B.16 is cleared.
GCR8B Default : 0010XXXXh
DRAM-Write control
Bit
Type
Function
31:24
Reserved
23:22
R/W
DRAM type select (DTYPE[1..0])
0 0
One 1M X 4
(10 X 10)
0 1
Two 1M X 4
(10 X 10)
1 0
4M X 4
(11 X 11)
1 1
4M X 4
(12 X 10)
21:20
R/W
MUXRA delay select
0 0
6 ns
0 1
10 ns (default)
1 0
14 ns
1 1
18 ns
19:18
Reserved
17
R/W
DRAM access mode 0 : mode 1 1 : mode 2
16
R/W
DRAM-Write transfer control 0 : Stop 1 : start (Effective when bit 17 =1)
15:2
R/W
DRAM-Write block length BL[15..2]
1:0
R
Reserved, Read as 1
n When DRAM-Write FIFO is not full ,ALS300 will generate a request to bus master
for data transfer until DRAM-Write FIFO is full. The bus master will transfer data
from ALS300 to system memory if enabled by bit 16.
oBlock length = (# of data byte ) - 1 (ex. 0FFFh→ 4K bytes)
ALS300 will generate an interrupt for every specified block size transfered.
pSW should detect DRAM type when system is power-on.
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