Avance Logic Inc.
ALS300
45
Part II : Specification for PCI I/F and Wave Engine
DRAM configuration :
11 X 11 : 4M X 4 (DTYPE[1,0]=10)
CASA#/CAS0# : A21,A9~ A0
CASB#/CAS1# : Inactive
RASA#/RAS# : A20,A19~ A0
12 X 10 : 4M X 4 (DTYPE[1,0]=11)
CASA#/CAS0# : A9~ A0
CASB#/CAS1# : Inactive
RASA#/RAS# : A21~ A10
10 X 10 : One 1M X 4 (DTYPE[1,0]=00)
CASA#/CAS0# : A9~ A0 (A20=0)
CASB#/CAS1# : A9~ A0 (A20=1)
RASA#/RAS# : A19~ A10
10 X 10 : Two 1M X 4 (DTYPE[1,0]=01)
CASA#/CAS0# : A9~ A0 (A20=0)
CASB#/CAS1# : A9~ A0 (A20=1)
RASA#/RAS# : A19~ A10
DRAM Access mode :
Mode 1 : DRAM is controlled by PCI DRAM controller.
Access : Memory Read/Write.
Mode 2 : DRAM is controlled by Wave engine.
Access : Program GCR8B to start bus master function. It support write function
only.
Arbitration between PCI D/A and SB D/A :
PCI/SB# ( Re-sample source select,GCR8C.28)
0
Select SB D/A (Default)
1
Select PCI D/A
PCI/SB#
PCI/SB# Toggle condition
1
SBVLID low go high edge
0
PCIVLID=1
Arbitration between OPL3 D/A and Wave Engine D/A :
WVE/FM# ( Re-sample source select,GCR8C.1)
0
Select OPL3 D/A (Default)
1
Select Wave Engine D/A
WVE/FM#
WVE/FM# Toggle condition
1
FMREQ low go high edge
0
(RAMW# low go high edge) |
(FMPWED#=0)
FIFO/Latch arrangement :
• AC97 serial output buffer :
Name
Size
Slot No.
Description
INDX
8 X 1
1
AC97 CMD/Address latch
DOUT
16 X 1
2
AC97 ouput data latch
PCILO
16 X 8
3
PCI playback left channel FIFO
PCIRO
16 X 8
4
PCI playback right channel FIFO
MOUT
16 X 1
5
Modem-Out latch
INDX connect to high byte of 16-bit bus
• AC97 serial input buffer :
Name
Size
Slot No.
Description
DIN
16 X 1
2
AC97 input data latch
PCILI
16 X 8
3
PCI record left channel FIFO
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