Avance Logic Inc.
ALS300
4
ROMCLK
O
111
91
E
2PROM clock
2mA TTL compatible CMOS output (Vt=1.7V)
ROMDOUT
I
114
93
E
2PROM serial data output
TTL compatible CMOS input (Vt=1.7V)
ROMDIN
O
112
92
E
2PROM serial data input
2mA TTL compatible CMOS output (Vt=1.7V)
Power/Ground :
17 pins
Pin Name
Type
P-160
P-128
Description
Characteristic Definition
VDD1
I
160
1
Digital power 5V
VDD2
I
21
19
Digital power 5V
VDD3
I
40
34
Digital power 5V
VDD4
I
60
52
Digital power 5V
VDD5
I
95
79
Digital power 5V
VDD6
I
108
89
Digital power 5V
VDD7
I
142
116
Digital power 5V
VDD8
I
121
101
Digital power 5V
AVDD
I
122
102
Analog power 5V
GND1
I
1
5
Digital Ground
GND2
I
24
22
Digital Ground
GND3
I
41
38
Digital Ground
GND4
I
80
65
Digital Ground
GND5
I
98
81
Digital Ground
GND6
I
116
95
Digital Ground
GND7
I
144
118
Digital Ground
AGND
I
124
104
Analog Ground
Bonding Option Pin :
1 pin
Pin Name
Type
Pin No
Description
Characteristic Definition
BOND
I
*
Bonding option pin
BOND = 0
160 QFP
1
128 QFP
Part I : Specification for SB Core Logic
Spec modified from ALS120 :
1.
Remove all recording command.
2.
No support IDE CDROM and MODEM
3.
Special MPU401 mode for internal Wave Engine.
4.
Remove analog block. (Substitute analog block by AC97 CODEC)
5.
All SB mixer write will generate an interrupt request via MXIRQ.
6.
Disable hardware power down pin.
7.
Add 128 bytes RAM for special MPU401 output.
8.
Remove Enhanced Game-Port.
ALS300 Power-on latch :
On power up reset ,ALS300 latch the following pin state. Their default state are :
Pin Name
Default state
MIDIOUT
Internal 50K
Ω pull high
ROMCS
Internal 50K
Ω pull low
After reset, pull high resistors will be disconnected from VCC and pull low resistor will disconnect
from GND. During the period of reset, the configuration register CR3 will latch those input pin state.
Please refer to CR3 definition to get details.
I/O Register Address:
ESP (enhanced sound processor):
BASE+6h
W
ESP-RESET-PORT
BASE+Ah
R
ESP-READ-DATA
BASE+Ch
W
ESP-COMMAND/DATA
BASE+Ch
R
ESP-WR-STATUS
BASE+Eh
R
ESP-RD-STATUS8
BASE+Fh
R
ESP-RD-STATUS16
BASE = P 'N P logical device 0 port 60.1,0 and port 61.7-4;
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