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HD64F36049 Datasheet(PDF) 155 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 155 Page - Renesas Technology Corp |
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155 / 562 page ![]() Section 9 I/O Ports Rev. 3.00 Mar. 15, 2006 Page 123 of 526 REJ09B0060-0300 • P30 pin Register PCR3 Bit Name PCR30 Pin Function Setting Value 0 P30 input pin 1 P30 output pin 9.4 Port 5 Port 5 is a general I/O port also functioning as an I 2C bus interface I/O pin, an A/D trigger input pin, and a wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.4. The register setting of the I 2C bus interface has priority for functions of the pins P57/SCL and P56/SDA. Since the output buffer for pins P56 and P57 has the NMOS push-pull structure, it differs from an output buffer with the CMOS structure in the high-level output characteristics (see section 23, Electrical Characteristics). P55/ WKP5/ADTRG P56/SDA P57/SCL P50/ WKP0 P54/ WKP4 P53/ WKP3 P52/ WKP2 P51/ WKP1 Port 5 Figure 9.4 Port 5 Pin Configuration Port 5 has the following registers. • Port mode register 5 (PMR5) • Port control register 5 (PCR5) • Port data register 5 (PDR5) • Port pull-up control register 5 (PUCR5) |
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