HD64F36049 datasheet(263/562 Pages) RENESAS

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Section 14 Timer Z

Rev. 3.00 Mar. 15, 2006 Page 231 of 526

REJ09B0060-0300

TIORC: TIORC selects whether GRC or GRD is used as an output compare register or an input

capture register. When an output compare register is selected, the output setting is selected. When

an input capture register is selected, an input edge of an input capture signal is selected. TIORC

also selects the function of FTIOC or FTIOD pin.

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 1.

IOD2

IOD1

IOD0

R/W

I/O Control D2 to D0

GRD is an output compare register:

000: Disables pin output by compare match

001: 0 output by GRD compare match

010: 1 output by GRD compare match

011: Toggle output by GRD compare match

GRD is an input capture register:

100: Input capture to GRD at the rising edge

101: Input capture to GRD at the falling edge

11X: Input capture to GRD at both rising and falling

edges



Reserved

This bit is always read as 1.

IOC2

IOC1

IOC0

R/W

I/O Control C2 to C0

GRC is an output compare register:

000: Disables pin output by compare match

001: 0 output by GRC compare match

010: 1 output by GRC compare match

011: Toggle Output by GRC compare match

GRC is an input capture register:

100: Input capture to GRC at the rising edge

101: Input capture to GRC at the falling edge

11X: Input capture to GRC at both rising and falling

edges

[Legend] X:

Don't care

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