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HD64F36049 Datasheet(PDF) 312 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 312 Page - Renesas Technology Corp |
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312 / 562 page ![]() Section 14 Timer Z Rev. 3.00 Mar. 15, 2006 Page 280 of 526 REJ09B0060-0300 3. Overflow Flag (OVF) Set Timing: The overflow flag is set to 1 when the TCNT overflows. Figure 14.50 shows the timing. OVF TCNT Overflow signal H'0000 H'FFFF ITMZ φ Figure 14.50 OVF Flag Set Timing 14.5.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 14.51 shows the timing in this case. Address TSR address φ WTSR (internal write signal) IMF, OVF ITMZ Figure 14.51 Status Flag Clearing Timing |
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