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HD64F36049 Datasheet(PDF) 316 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 316 Page - Renesas Technology Corp |
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316 / 562 page ![]() Section 14 Timer Z Rev. 3.00 Mar. 15, 2006 Page 284 of 526 REJ09B0060-0300 5. Contention between GR Read and Input Capture: If an input capture signal is generated in the T 1 state of a GR read cycle, the data that is read will be transferred before input capture transfer. Figure 14.56 shows the timing in this case. T 1 T 2 GR GR read cycle GR address Internal read signal Input capture signal Internal data bus X X M φ Figure 14.56 Contention between GR Read and Input Capture |
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