SH7101 datasheet(101/486 Pages) RENESAS

101 / 486 page

6. Interrupt Controller (INTC)

Rev.2.00 Sep. 27, 2007 Page 67 of 448

REJ09B0394-0200

Section 6 Interrupt Controller (INTC)

The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt

requests to the CPU.

6.1

Features

• 16 levels of interrupt priority

• NMI noise canceler function

• Occurrence of interrupt can be reported externally (IRQOUT pin)

Figure 6.1 shows a block diagram of the INTC.

IRQOUT

NMI

IRQ0

IRQ1

IRQ2

IRQ3

MTU

CMT

A/D

SCI

WDT

I/O

(Interrupt request)

Input

control

Com-

parator

Interrupt

request

CPU

I3 I2 I1 I0

Bus

interface

IPRA to IPRI

ICR1

ISR

ICR2

Module bus

INTC

IPR

MTU

CMT

A/D

SCI

WDT

Legend:

: Multifunction timer unit

: Compare match timer

: A/D converter

: Serial communications interface

: Watchdog timer

I/O

ICR1, ICR2

ISR

IPRA, IPRD to IPRI

: I/O port (Port output controller)

: Interrupt control register

: IRQ status register

: Interrupt priority registers A, D to I

: Status register

Figure 6.1 INTC Block Diagram

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