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SH7101 Datasheet(PDF) 102 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 102 Page - Renesas Technology Corp |
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102 / 486 page  6. Interrupt Controller (INTC) Rev.2.00 Sep. 27, 2007 Page 68 of 448 REJ09B0394-0200 6.2 Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbreviation I/O Function Non-maskable interrupt input pin NMI I Input of non-maskable interrupt request signal Interrupt request input pins IRQ0 to IRQ3 I Input of maskable interrupt request signals Interrupt request output pin IRQOUT O Output of notification signal when an interrupt has occurred 6.3 Register Descriptions The interrupt controller has the following registers. For details on register addresses and register states during each processing, refer to section 18, List of Registers. • Interrupt control register 1 (ICR1) • Interrupt control register 2 (ICR2) • IRQ status register (ISR) • Interrupt priority register A (IPRA) • Interrupt priority register D (IPRD) • Interrupt priority register E (IPRE) • Interrupt priority register F (IPRF) • Interrupt priority register G (IPRG) • Interrupt priority register H (IPRH) • Interrupt priority register I (IPRI) |
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