SH7101 datasheet(105/486 Pages) RENESAS

105 / 486 page

6. Interrupt Controller (INTC)

Rev.2.00 Sep. 27, 2007 Page 71 of 448

REJ09B0394-0200

Bit

Bit Name

Initial

Value

R/W

Description

IRQ1ES1

IRQ1ES0

R/W

This bit sets the IRQ1 interrupt request edge detection

mode.

00: Interrupt request is detected on falling edge of

IRQ1

input

01: Interrupt request is detected on rising edge of

IRQ1

input

10: Interrupt request is detected on both of falling and

rising edge of

IRQ1 input

11: Cannot be set

IRQ2ES1

IRQ2ES0

R/W

This bit sets the IRQ2 interrupt request edge detection

mode.

00: Interrupt request is detected on falling edge of

IRQ2

input

01: Interrupt request is detected on rising edge of

IRQ2

input

10: Interrupt request is detected on both of falling and

rising edge of

IRQ2 input

11: Cannot be set

IRQ3ES1

IRQ3ES0

R/W

This bit sets the IRQ3 interrupt request edge detection

mode.

00: Interrupt request is detected on falling edge of

IRQ3

input

01: Interrupt request is detected on rising edge of

IRQ3

input

10: Interrupt request is detected on both of falling and

rising edge of

IRQ3 input

11: Cannot be set

7 to 0

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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