SH7101 datasheet(104/486 Pages) RENESAS

104 / 486 page

6. Interrupt Controller (INTC)

Rev.2.00 Sep. 27, 2007 Page 70 of 448

REJ09B0394-0200

Bit

Bit Name

Initial

Value

R/W

Description

IRQ3S

R/W

IRQ3 Sense Select

This bit sets the IRQ3 interrupt request detection mode.

0: Interrupt request is detected on low level of IRQ3 input

1: Interrupt request is detected on edge of IRQ3 input

(edge direction is selected by ICR2)

3 to 0

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

6.3.2

Interrupt Control Register 2 (ICR2)

ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins

IRQ0

IRQ3. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the

edge detection mode by the sense select bits of IRQ0 to IRQ 3 in Interrupt control register 1

(ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the

setting of ICR2 is ignored.

Bit

Bit Name

Initial

Value

R/W

Description

IRQ0ES1

IRQ0ES0

R/W

This bit sets the IRQ0 interrupt request edge detection

mode.

00: Interrupt request is detected on falling edge of

IRQ0

input

01: Interrupt request is detected on rising edge of

IRQ0

input

10: Interrupt request is detected on both of falling and

rising edge of

IRQ0 input

11: Cannot be set

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