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SH7101 Datasheet(PDF) 308 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 308 Page - Renesas Technology Corp |
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308 / 486 page  9. Watchdog Timer Rev.2.00 Sep. 27, 2007 Page 274 of 448 REJ09B0394-0200 Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFF8612. It cannot be written by byte transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 9.7. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. 15 8 7 0 15 8 7 0 H'A5 H'5A Write data • Writing 0 to the WOVF bit • Writing to the RSTE and RSTS bits Address: H'FFFF8612 Address: H'FFFF8612 H'00 Figure 9.7 Writing to RSTCSR Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for TCSR, H'FFFF8611 for TCNT, and H'FFFF8613 for RSTCSR. |
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