SH7101 datasheet(305/486 Pages) RENESAS

305 / 486 page

9. Watchdog Timer

Rev.2.00 Sep. 27, 2007 Page 271 of 448

REJ09B0394-0200

9.4.2

Interval Timer Mode

To use the WDT as an interval timer, clear WT/

IT to 0 and set TME to 1 in TCSR. An interval

timer interrupt (ITI) is generated each time the timer counter (TCNT) overflows. This function can

be used to generate interval timer interrupts at regular intervals.

TCNT value

H'FF

H'00

Overflow

WT/

IT = 0

TME = 1

Overflow

ITI

Time

Legend:

ITI: Interval timer interrupt request generation

Figure 9.3 Operation in Interval Timer Mode

9.4.3

Clearing Software Standby Mode

The watchdog timer has a special function to clear software standby mode with an NMI interrupt

or IRQ0 to IRQ3 interrupts. When using software standby mode, set the WDT as described below.

Before Transition to Software Standby Mode: The TME bit in TCSR must be cleared to 0 to

stop the watchdog timer counter before entering software standby mode. The chip cannot enter

software standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in TCSR so that the

counter overflow interval is equal to or longer than the oscillation settling time. See section 19.3,

AC Characteristics, for the oscillation settling time.

Recovery from Software Standby Mode: When an NMI signal or

IRQ0 to IRQ3 signals are

received in software standby mode, the clock oscillator starts running and TCNT starts

incrementing at the rate selected by bits CKS2 to CKS0 before software standby mode was

entered. When TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable

and usable; clock signals are supplied to the entire chip and software standby mode ends.

For details on software standby mode, see section 17, Power-Down Modes.

SH7101 Datasheet(PDF) 305 Page - Renesas Technology Corp