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SH7101 Datasheet(PDF) 301 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 301 Page - Renesas Technology Corp |
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301 / 486 page  9. Watchdog Timer Rev.2.00 Sep. 27, 2007 Page 267 of 448 REJ09B0394-0200 Bit Bit Name Initial Value R/W Description 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Select one of eight internal clock sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system clock ( φ). The overflow frequency for φ = 40 MHz is enclosed in parentheses* 3. 000: Clock φ/2 (frequency: 12.8 μs) 001: Clock φ/64 (frequency: 409.6 μs) 010: Clock φ/128 (frequency: 0.8 ms) 011: Clock φ/256 (frequency: 1.6 ms) 100: Clock φ/512 (frequency: 3.3 ms) 101: Clock φ/1024 (frequency: 6.6 ms) 110: Clock φ/4096 (frequency: 26.2 ms) 111: Clock φ/8192 (frequency: 52.4 ms) Notes: 1. Only a 0 can be written after reading 1. 2. Section 9.3.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in watchdog timer mode. 3. The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. |
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