SH7101 datasheet(303/486 Pages) RENESAS

303 / 486 page

9. Watchdog Timer

Rev.2.00 Sep. 27, 2007 Page 269 of 448

REJ09B0394-0200

9.4

Operation

9.4.1

Watchdog Timer Mode

To use the WDT as a watchdog timer, set the WT/

IT and TME bits of TCSR to 1. Software must

prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow

occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails

to be rewritten and overflows occur due to a system crash or the like, a

WDTOVF signal is output

externally. The

WDTOVF signal can be used to reset the system. The WDTOVF signal is output

for 128

φ clock cycles.

If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally

simultaneous to the

WDTOVF signal when TCNT overflows. Either a power-on reset or a manual

reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512

clock cycles.

When a WDT overflow reset is generated simultaneously with a reset input at the

RES pin, the

RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0.

The following are not initialized by a WDT reset signal:

• POE (port output enable) of MTU registers

• PFC (pin function controller) registers

• I/O port registers

These registers are initialized only by an external power-on reset.

SH7101 Datasheet(PDF) 303 Page - Renesas Technology Corp