SH7101 datasheet(300/486 Pages) RENESAS

300 / 486 page

9. Watchdog Timer

Rev.2.00 Sep. 27, 2007 Page 266 of 448

REJ09B0394-0200

9.3.2

Timer Control/Status Register (TCSR)

TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be

input to TCNT, and the timer mode.

Bit

Bit Name

Initial Value

R/W

Description

OVF

R/(W)*

Overflow Flag

Indicates that TCNT has overflowed in interval timer

mode. Only a write of 0 is permitted, to clear the

flag. This flag is not set in watchdog timer mode.

[Setting condition]

• When TCNT overflows in interval timer mode.

[Clearing conditions]

• Cleared by reading OVF

• When 0 is written to the TME bit in interval timer

mode

WT/

R/W

Timer Mode Select

Selects whether the WDT is used as a watchdog

timer or interval timer. When TCNT overflows, the

WDT either generates an interval timer interrupt (ITI)

or generates a

WDTOVF signal, depending on the

mode selected.

0: Interval timer mode

Interval timer interrupt (ITI) request to the CPU

when TCNT overflows

1: Watchdog timer mode

WDTOVF signal output externally when TCNT

overflows*

TME

R/W

Timer Enable

Enables or disables the timer.

0: Timer disabled

TCNT is initialized to H'00 and count-up stops

1: Timer enabled

TCNT starts counting. A

WDTOVF signal or

interrupt is generated when TCNT overflows.

4, 3

⎯

All 1

Reserved

This bit is always read as 1, and should only be

written with 1.

SH7101 Datasheet(PDF) 300 Page - Renesas Technology Corp

SH7101 Datasheet(HTML) 300 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL