SH7101 datasheet(298/486 Pages) RENESAS

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9. Watchdog Timer

Rev.2.00 Sep. 27, 2007 Page 264 of 448

REJ09B0394-0200

Overflow

Interrupt

control

ITI (interrupt

request signal)

Internal reset

signal*

Reset

control

RSTCSR

TCNT

TSCR

φ/2

φ/64

φ/128

φ/256

φ/512

φ/1024

φ/4096

φ/8192

Clock

select

Internal clock

sources

Bus

interface

Module bus

WDT

Legend:

TCSR:

Timer control/status register

TCNT:

Timer counter

RSTCSR: Reset control/status register

Note: * The internal reset signal can be generated by making a register setting.

Power-on reset or manual reset can be selected.

WDTOVF

Figure 9.1 Block Diagram of WDT

9.2

Input/Output Pin

Table 9.1 shows the pin configuration of the watchdog timer.

Table 9.1

Pin Configuration

Abbreviation

I/O

Function

Watchdog timer overflow

WDTOVF

Outputs the counter overflow signal in

watchdog timer mode

Note:

The

WDTOVF pin should not be pulled down. However, if it is necessary to pull this pin

down, a resistance of 1 M

Ω or higher should be used.

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