SH7101 datasheet(307/486 Pages) RENESAS

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9. Watchdog Timer

Rev.2.00 Sep. 27, 2007 Page 273 of 448

REJ09B0394-0200

9.5

Interrupt Source

During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The

interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be

cleared to 0 in the interrupt handling routine.

Table 9.2

WDT Interrupt Source (in Interval Timer Mode)

Name

Interrupt Source

Interrupt Flag

ITI

TCNT overflow

OVF

9.6

Usage Notes

9.6.1

Notes on Register Access

The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being

more difficult to write to. The procedures for writing to and reading these registers are given

below.

Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.

They cannot be written by byte transfer instructions.

TCNT and TCSR both have the same write address. The write data must be contained in the lower

byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure

9.6). This transfers the write data from the lower byte to TCNT or TCSR.

H'5A

H'A5

Write data

• Writing to TCNT

• Writing to TCSR

Address: H'FFFF8610

Figure 9.6 Writing to TCNT and TCSR

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