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SH7101 Datasheet(PDF) 309 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  486 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 309 Page - Renesas Technology Corp

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9. Watchdog Timer
Rev.2.00 Sep. 27, 2007 Page 275 of 448
REJ09B0394-0200
9.6.2
TCNT Write and Increment Contention
If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT,
the write takes priority and the timer counter is not incremented. Figure 9.8 shows this operation.
Address
φ
Internal write
signal
TCNT input
clock
TCNT
N
M
T1
T2
TCNT write cycle
Counter write data
T3
TCNT address
Figure 9.8 Contention between TCNT Write and Increment
9.6.3
Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while
the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by
clearing the TME bit to 0) before rewriting the values of bits CKS2 to CKS0.
9.6.4
Changing between Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.



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