3886 datasheet(273/380 Pages) RENESAS

273 / 380 page

2-156

3886 Group User’s Manual

APPLICATION

2.14 Processor mode

Figures 2.14.4 to 2.14.6 show the basic timing at 8 MHz (no wait) operating.

Fig. 2.14.4 Read cycle (OE access, SRAM)

Fig. 2.14.5 Read cycle (OE access, EPROM)

50 ns (max.)

65 ns (min.)

A0 to A7

(Port P0)

A8 to A14

(Port P1)

Data

DQ1 to DQ8

(Port P2)

(AD15)

(3886 group’s WR)

“H” level

125 ns—10 ns (min.)

125ns—40 ns (min.)

(3886 group’s RD)

td(AL–RD)

tWL(RD)

ta(OE)

tsu(DB—RD)

td(AL—RD)

: RD delay time after address output of 3886 group

tWL(RD)

: RD pulse width of 3886 group

ta(OE)

: Output enable access time of M5M5256BP

tsu(DB—RD) : Data bus set up time before RD of 3886 group

Low-order address

High-order address

50 ns (max.)

65 ns (min.)

A0 to A7

(Port P0)

A8 to A14

(Port P1)

Data

D0 to D7

(Port P2)

5.8 ns (max.)

tPHL

125 ns—10 ns (min.)

125 ns—40 ns (min.)

(3886 group’s RD)

td(AL—RD)

tWL(RD)

ta(OE)

tsu(DB—RD)

tPHL

: Output delay time of 74F04

td(AL—RD)

: RD delay time after address output of 3886 group

tWL(RD)

: RD pulse width of 3886 group

ta(OE)

: Output enable access time of M5M27C256AK

tsu(DB—RD) : Data bus set up time before RD of 3886 group

Low-order address

High-order address

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