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3886 Datasheet(PDF) 274 Page - Renesas Technology Corp |
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3886 Datasheet(HTML) 274 Page - Renesas Technology Corp |
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274 / 380 page ![]() 3886 Group User’s Manual APPLICATION 2-157 2.14 Processor mode Fig. 2.14.6 Write cycle (W control, SRAM) td(AL—WR): WR delay time after address output of 3886 group tWL(WR): WR pulse width of 3886 group td(WR—DB): Data bus delay time after WR of 3886 group tsu(D): Data set up time of M5M5256BP 65 ns (max.) 35 ns (min.) Data DQ1 to DQ8 (Port P2) S (AD15) OE (3886 group’s RD) “H” level 125 ns—10 ns (min.) 125 ns—40 ns (min.) W (3886 group’s WR) td(AL—WR) tWL(WR) td(WR—DB) tsu(D) A0 to A7 (Port P0) A8 to A14 (Port P1) Low-order address High-order address |
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