3886 datasheet(277/380 Pages) RENESAS

277 / 380 page

2-160

3886 Group User’s Manual

APPLICATION

2.14 Processor mode

Figures 2.14.9 to 2.14.11 show the basic timing at 9 MHz (no wait) operating.

Fig. 2.14.9 Read cycle (OE access, SRAM)

Fig. 2.14.10 Read cycle (OE access, EPROM)

35 ns (max.)

50 ns (min.)

A0 to A7

(Port P0)

High-order address

A8 to A14

(Port P1)

Data

DQ1 to DQ8

(Port P2)

(AD15)

“H” level

111 ns—10 ns (min.)

111 ns—40ns (min.)

(3886 group’s RD)

td(AL—RD)

tWL(RD)

ta(OE)

tsu(DB—RD)

td(AL—RD): RD delay time after address output of 3886 group

tWL(RD): RD pulse width of 3886 group

ta(OE): Output enable access time of M5M5256BP

tsu(DB—RD): Data bus set up time before RD of 3886 group

Low-order address

45 ns (max.)

50 ns (min.)

A0 to A7

(Port P0)

High-order address

A8 to A14

(Port P1)

Data

D0 to D7

(Port P2)

“H” level

5.8 ns (max.)

tPHL

111 ns—10ns (min.)

111 ns—40 ns (min.)

(3886 group’s RD)

td(AL—RD)

tWL(RD)

ta(OE)

tsu(DB—RD)

tPHL

: Output delay time of 74F04

td(AL—RD): RD delay time after address output of 3886 group

tWL(RD): RD pulse width of 3886 group

ta(OE): Output enable access time of M5M27C256AK

tsu(DB—RD): Data bus set up time before RD of 3886 group

Low-order address

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