3886 datasheet(291/380 Pages) RENESAS

291 / 380 page

2-174

3886 Group User’s Manual

APPLICATION

2.15 Flash memory

Fig. 2.15.13 CPU reprogramming control program example (4)

YES

Issue program command

Reprogramming data is written

to program address

YES

PASS

FAIL

YES

12 V applied circuit

to VPP “OFF”

➄ CPU reprogramming mode release

Initialize watchdog timer (write to

watchdog timer control register) to

prevent generation of watchdog timer

interrupt during this processing.

Retry counter + 1

YES

➃ Program/program verify

Initialize watchdog timer (write to

watchdog timer control register) to

prevent generation of watchdog

timer interrupt during this

processing.

YES

END

YES

Program address + 1

Set program start address

Continued from “CPU reprogramming control

program example (2)” on page before previous

Initialization of software counter

(retry counter) for reprogramming

retry count = “0”

Reprogramming data receive

from serial I/O

Wait 1

µs *1

Erase/program

busy flag = “0” ?

Issue program verify command

Wait 6

µs *1

Program verify

data check

Program last address

Port Pi1 = “0”

Apply VPP voltage = VPPL

waiting for stabilizing *2

CPU reprogramming

mode monitor flag

= “0” ?

Wait 5 ms *3

CPU reprogramming mode

select bit = “0”

CPU reprogramming

mode select bit

= “0”

Waiting for release of CPU

reprogramming mode

CPU reprogramming

mode select bit

= “0”

CPU reprogramming error

CPU reprogramming

mode select bit = “0”

CPU reprogramming

mode monitor flag

= “0” ?

Wait 5 ms *3

Port Pi1 = “0”

Apply VPP voltage = VPPL

waiting for stabilizing *2

Retry counter

= 25?

“4016” is written to flash

command register

(address 0FFF16)

“C016” is written to flash

command register

(address 0FFF16)

Waiting for program

completed

*1: The wait processing time shown in the flow chart is required regardless of the external clock input frequency.

*2: Waiting by software until VPP input voltage is stabilized at VPPL is recommended. (Refer to Figure 2.15.14 and

Figure 2.15.15 VPP voltage control timing B.)

*3: The waiting time depends on VPP control circuit (Refer to Figure 2.15.14 and Figure 2.15.15 VPP voltage control

timing C.)

3886 Datasheet(PDF) 291 Page - Renesas Technology Corp

3886 Datasheet(HTML) 291 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL